1. Field of the Invention
The present invention generally relates to a nonvolatile semiconductor memory device using trench isolation. The present invention also relates to a method of manufacturing such a nonvolatile semiconductor memory device.
2. Description of the Background Art
FIG. 12 is a plan view of a conventional nonvolatile semiconductor device using trench isolation. FIG. 13 is a cross section taken along the line A--A of FIG. 12. FIG. 14 is a cross section taken along the line B--B of FIG. 12.
Referring to these figures, the conventional nonvolatile semiconductor memory device includes a semiconductor substrate 101. On a main surface of semiconductor substrate 101, trenches 105 for trench isolation are formed as lines. A thick oxide film 106 is provided on semiconductor substrate 101 to fill trench 105. Trench isolation is provided by trench 105 and thick oxide film 106 filled therein. On semiconductor substrate 101 on both sides of trench 105, a floating gate 103 is formed, with a tunnel oxide film 102 interposed. On floating gate 103, a control gate 109 is provided, with an interpoly insulation film 108 interposed.
Referring to FIG. 15, operation of the nonvolatile semiconductor memory device will be described. Here, the method of Channel Hot Electron writing, Fowler-Nordheim tunneling current erasure, which are common in the 1M to 16M first generation will be described.
Information is stored dependent on whether the floating gate is charged or not. When electrons are injected to the floating gate and the gate is charged negative, Vth viewed from the control gate thereon becomes higher (writing state). By contrast, when the floating gate is not charged negative, Vth is low (erased stated). Stored content can be read by determining whether or not the transistor turns ON when a potential intermediate between these Vth values is applied to the control gate.
Writing can be done on a per byte basis by selecting drain interconnection and gate interconnection. However, selective application of erasing voltage is not possible. Therefore, erasure has to be done on all the bits simultaneously.
Since the floating gate electrode is surrounded by an insulating film of high quality, injected electrons remain in the electrode unless they are erased. Therefore, the stored content is maintained even when power is turned off.
A method of manufacturing a conventional nonvolatile semiconductor memory device using trench isolation will be described in the following.
Referring to FIG. 16, tunnel oxide film 102 is formed on the surface of a semiconductor substrate (silicon semiconductor substrate) 101 and floating gate 103 is deposited on tunnel oxide film 102. Floating gate 103 is generally formed using polycrystalline silicon containing an impurity such as P (phosphorus) as its material. Thereafter, using photolithography, a resist pattern 104 having a desired width of removal x1 and width of remaining portion x2 along the direction X is formed.
Referring to FIGS. 17 and 18, using resist pattern 104 as an etching mask, floating gate 103, tunnel oxide film 102 and the surface of silicon semiconductor substrate 101 are successively dry etched. A trench having a desired depth y is formed in silicon semiconductor substrate 101, thus forming trench 105. FIG. 17 show a state in the middle of the process. FIG. 18 shows the state at the end of dry etching.
Referring to FIG. 19, thick oxide film 106 is deposited on silicon semiconductor substrate 101 to fill trench 105.
Referring to FIGS. 19 and 20, thick oxide film 106 is removed by CMP (Chemical Mechanical Polishing), using floating gate 103 as a stopper film or dry etch, until the position of the upper surface of thick oxide film 106 becomes flush with the upper surface of floating gate 103. Consequently, thick oxide film 106 fills trench 105, and trench isolation 107 having the width of isolation x1 is completed.
Referring to FIG. 21, interpoly insulation film 108 and control gate 109 are deposited successively.
Thereafter, referring to FIGS. 12 and 21, control gate 109 is etched to have a desired width of removal and desired width of the remaining portion along the direction Y orthogonal to the direction X, using interpoly insulation film 108 therebelow as a stopper film (the change does not appear in FIG. 21). Thereafter, interpoly insulation film 108 and floating gate 103, which are exposed at the portion where control gate 109 is removed by etching, are etched, and a memory cell 110 of a nonvolatile semiconductor memory device is completed. The width of floating gate 103 of the thus formed memory cell 110 is x2, as shown in FIG. 21.
The first problem experienced by the conventional nonvolatile semiconductor memory device (first prior art example) manufactured through the method shown in FIGS. 16 to 21 will be described in the following.
Currently, market for portable telephone, digital still camera and so on for which nonvolatile semiconductor memory device is used has been ever widening. Therefore, demand for the nonvolatile semiconductor memory devices has been increased, and increased storage capacity has been required. In order to increase storage capacity of the nonvolatile semiconductor memory device, increase in the chip size must be minimized. The reason is that PDAs (Personal Digital Assistant) such as personal telephones and digital still camera for which the memory device is used are mostly compact and handy, and hence the nonvolatile semiconductor memory device as an LSI (Large Scale Integrated Circuit) used as the component must also be small in size. Unless the size of memory cell 110, that is, width x2 of floating gate 103, width x1 of trench isolation, the width of control gate 109 and so on is much reduced, the product could not be commercially competitive in view of cost.
However, when the width of removal x1 and the width of the remaining portion x2 of resist pattern 104 from which the width x1 of trench isolation 107 and width x2 of floating gate 103 are defined come nearer to the resolution of photolithography, it becomes difficult to form resist pattern 104 having desired width of removal x1 and the width of the remaining portion x2 having good shape as shown in FIG. 16. With resist pattern 104 of unsatisfactory shape not having desired width of removal and the width of the remaining portion, the target width x1 of trench isolation 107 and target width x2 of floating gate 103 cannot be obtained. In the worst case, memory cell 110 may not function normally.
In such a case, the thickness of resist itself may be reduced, so as to form resist pattern 104 having a good shape with desired width of removal x1 and desired width of the remaining portion x2. However, in that case, when a trench having a desired depth y is etched in silicon semiconductor substrate 101 and trench 105 is formed, there is not the resist 104 left thereon, as shown in FIG. 18. As a result, floating gate 103 shown in FIG. 18 is etched and, as a result, it becomes thinner than floating gate 103 shown in FIG. 16. The silicon semiconductor substrate 101 is formed of silicon single crystal and generally, floating gate 103 is formed of polycrystalline silicon which is the same element as silicon semiconductor substrate 101. Therefore, under the etching condition for etching silicon semiconductor substrate 101, that is, silicon single crystal, the floating gate 103 tends to be etched as it is formed of polycrystalline silicon. Therefore, as soon as resist pattern 104 is removed, floating gate 103 is subjected to etching. As a result, floating gate 103 can still have thin film thickness as shown in FIG. 18 and the surface of floating gate 103 and inner portion of floating gate 103 near the surface may be damaged by plasma used for dry etching.
Further, even when resist pattern 104 having good shape with desired width of removal x1 and desired width of the remaining portion x2 (such as shown in FIG. 16) could be resolved with thick resist film, resist pattern 104 would still be removed completely before forming trench 105 of the desired depth y, if the ratio of etching rate of films to be dry etched in forming trench 105 (that is, floating gate 103, tunnel oxide film 102 and silicon semiconductor substrate 101) and the etching rate of resist pattern 104 is small. This may result in dry etching of floating gate 103. Consequently, floating gate 103 comes to have thin film thickness as shown in FIG. 18, and as described above, the surface of floating gate 103 and inner portion of floating gate 103 near the surface are damaged by the plasma for dry etching.
Referring to FIGS. 19 and 20, when thick oxide film 106 deposited in trench 105 or floating gate 103 is to be removed by the CMP method so as to fill trench 105 with thick oxide film 106, floating gate 103 is made thinner to be the thin floating gate 103 as shown in FIG. 20, since the etching rate of floating gate 103 formed of polycrystalline silicon under the CMP method is faster than the etch rate of thick oxide film 106 under the CMP method. At this time, floating gate 103 is not only physically etched by the CMP method but it has its surface exposed to an alkali solution used in the CMP. Therefore, the upper surface of floating gate 103 and inner portion of floating gate 103 near the upper surface are physically and chemically damaged.
When thick oxide film 106 is to be filled in trench 105 not by the CMP method but by dry etch back method, the upper surface of floating gate 103 is exposed to etching plasma in the dry etch back method. Therefore, the upper surface of floating gate 103 and inner portion of floating gate 103 near the upper surface suffer from plasma damage of dry etching.
The conventional nonvolatile semiconductor memory device manufactured through the steps shown FIGS. 16 to 21 also has the following second problem.
Referring to FIG. 18, while floating gate 103, tunnel oxide film 102 and silicon semiconductor substrate 101 are being etched for forming trench 105, resist pattern 104 is also etched at the same time. Therefore, the surface of floating gate 103 and inside of the trench formed in silicon semiconductor substrate 101 are contaminated by carbon or the like coming out from the resist mainly formed of an organic substance.
As described above, in the nonvolatile semiconductor memory device manufactured by the method shown in FIGS. 16 to 21, the surface of floating gate 103 and inner portion of floating gate 103 near the surface are damaged by the etching plasma during dry etching when the trench is formed. The floating gate is physically damaged by etching and chemically damaged by alkali solution (in case of CMP method) or damaged at the upper surface of floating gate 103 and inner portion of floating gate 103 near the upper surface by etching plasma (in case of dry etching back method), when the thick oxide film is etched by the CMP method or dry etch back method. These damages have undesirable influence on the subsequently formed interpoly insulation film. This may possibly leads to unsatisfactory retention which is one of the defective modes of the nonvolatile semiconductor memory device.
Further, when the trench is formed, the resist pattern is also etched simultaneously. Therefore, contaminant such as carbon which is a main component of the resist adheres on the side wall or a bottom portion of the trench formed in silicon semiconductor substrate and on the surface of the floating gate. The contaminant such as carbon which is a main component of the resist may enter the inner portion of the floating gate near the surface of the floating gate, and inner portion of the silicon semiconductor substrate near side walls and bottom surfaces of a trench formed in the silicon semiconductor substrate, because of knocking by the etching particles. The contaminant such as carbon which entered the inner portion near the surface of the floating gate has undesirable influence on the subsequently formed interpoly insulation film, causes unsatisfactory retention. The contaminant such as carbon adheres on the side wall or bottom portion of the trench formed in the silicon semiconductor substrate and the contaminant such as carbon which entered the inner portion near the surface of the side wall or the bottom portion of the trench causes the impurity defect, degrading junction breakdown voltage or forming a leak current path, which may degrade capability of isolation (punch-through margin) between adjacent memory cells.
A second prior art example will be described in the following. The second prior art example which will be described in the following has been proposed to avoid plasma damage at the time of dry etching and physical and chemical damages by the CMP method on the floating gate and to avoid contamination by carbon or the like in the trench formed in the silicon semiconductor substrate and the surface of floating gate, experienced in the first prior art example.
Referring to FIG. 22, a tunnel oxide film 202 is formed on a surface of a silicon semiconductor substrate 201, and a floating gate 203 is deposited with a tunnel oxide film 202 interposed. Thereafter, a silicon nitride film 211 of which etching rate under the CMP method is slower than the oxide film is deposited on floating gate 203. Silicon nitride film 211 serves as a stopper film in the CMP method and a hard mask at the time of etching of trench 205 as will be described later. Here, the term hard mask is opposed to term resist mask (which is formed of an organic substance), and the hard mask refers to an etching mask of which main component is not an organic substance but an inorganic substance. Thereafter, by photolithography, a resist pattern 204 having a desired width x1 for removal and x2 to be left along the direction X is formed in good shape.
Referring to FIGS. 22 and 23, using resist pattern 204 as an etching mask, silicon nitride film 211 is dry etched, so that silicon nitride film 211 of a good shape having a desired width x1 for removal and desired width x2 to be left is formed.
Referring to FIG. 24, using silicon nitride film 211 as a hard mask, a trench having a desired depth y is formed in silicon semiconductor substrate 201 by successively dry etching floating gate 203, tunnel oxide film 202, and silicon semiconductor substrate 201, and thus trench 205 is formed.
At this time, as shown in FIG. 24, the hard mask formed of an inorganic substance, that is, silicon nitride film 211 is also made thinner to some extent. The reason for this is that the etching rate of tunnel oxide film 202 formed of an oxide of silicon element in dry etching is not much different from the etching rate of silicon nitride film which is a material of the hard mask in dry etching, or that it is difficult to find an etching condition which can differentiate the etching rates. Accordingly, when tunnel oxide film 202 is etched, silicon nitride film 211 shown in FIG. 23 is also etched to some extent.
However, contamination of the surface of floating gate 103 and in the trench 105 formed in silicon semiconductor substrate 101 experienced in the first prior art example and shown in FIG. 18 can be avoided as a hard mask formed of an inorganic substance, that is, silicon nitride film 211, is used. Further, since there is a floating gate 203 below silicon nitride film 211, floating gate 203 is not etched during dry etching. Therefore, floating gate 203 is not made thin, and floating gate 203 is free from plasma damage during dry etching. Referring to FIG. 25, thick oxide film 206 is deposited on silicon semiconductor substrate 101 until trench 205 is filled.
Referring to FIGS. 25 and 26, thick oxide film 206 is removed until the position of the upper surface of thick oxide film 206 is flush with the upper surface of silicon nitride film 211, using silicon nitride film 211 as a stopper film of the CMP method, so that trench 205 is filled with thick oxide film 206. The step shown in FIG. 26 shows removal of thick oxide film 206 by the CMP method. However, thick oxide film 206 may be filled in trench 205 by dry etch back method.
At this time, since silicon nitride film 211 of which etching rate in the CMP method is slower than that of the oxide film functions as a stopper film in the CMP method and there is floating gate 203 below silicon nitride film 211, floating gate 203 is not etched and is not made thin in the CMP method. Therefore, floating gate 203 is neither physically damaged by etching in CMP method nor damaged chemically by the alkali solution.
The same applies to the case where thick oxide film 206 is filled in trench 205 by dry etch back method. More specifically, even when dry etch back method is used, the upper surface of floating gate 203 is not exposed to etching plasma, and therefore the upper surface of floating gate 203 and inner portion of floating gate 203 ear the upper surface are not damaged by plasma during etching.
In FIG. 26, silicon nitride film 211 is shown considerably thinner than silicon nitride film 211 of FIG. 25. This shows that etching is performed considerably by the CMP method so as to sufficiently remove thick oxide film 206 and accordingly silicon nitride film 211 is also made thin, by the CMP method. Though silicon nitride film 211 is made thinner, floating gate 203 is not made thinner. Further, floating gate 203 is not physically or chemically damaged by the CMP method.
Referring to FIG. 27, unnecessary silicon nitride film 211 is removed. Silicon nitride film 211 is removed by hot phosphoric acid. The reason for this is that when silicon nitride film 211 is removed by dry etching, floating gate 203 is damaged by the plasma during dry etching.
At this time, floating gate 203 formed of polycrystalline silicon and including impurity such as P is exposed to hot phosphoric acid. Therefore, the surface of floating gate 203 is made rough, and comes to have small recesses and protrusions.
Referring to FIGS. 27 and 28, the upper surface of thick oxide film 206 protruding upward than the surface of floating gate 203 is wet etched by the thickness w by hydrofluoric acid solution, and the upper surface of thick oxide film 206 is made lower by the thickness z than the upper surface of the floating gate 203. Thus, thick oxide film 206 is filed in trench 205, and trench isolation 207 having the isolation width x1 is completed.
Referring to FIG. 29, interpoly insulation film 208 and control gate 209 are deposited successively. Thereafter, control gate 209 is etched to have desired width for removal and desired width to be left in a direction Y orthogonal to the direction X, using the underlying interpoly insulation film 208 as a stopper film. Thereafter, interpoly insulation film 208 and floating gate 203 exposed at portions where control gate 209 is etched, and a memory cell 210 of the nonvolatile semiconductor memory device is formed. The width of the floating gate 203 of the thus formed memory cell 210 is x2.
Referring to FIG. 29, the reason why the upper surface of thick oxide film 206 is made lower by the thickness z than the upper surface of floating gate 203 will be described.
A nonvolatile semiconductor memory device such as an EPROM, EEPROM and a flash memory controls amount of charges in floating gate 203 and information represented by two values, that is "0" and "1" is stored dependent on whether the threshold voltage of memory cell 210 is high or low (the threshold voltage is generally represented by the reference character Vth, which means the control gate voltage V.sub.cg at the time when a certain current flows to the channel of semiconductor substrate 201 by application of a voltage to control gate 209).
FIG. 31 is a schematic equivalent circuit diagram of memory cell 210 shown in FIG. 29. The equivalent circuit of memory cell 210 shown in FIG. 31 is represented by a series connection of a capacitance Ccf213 between control gate 209 and floating gate 203 and capacitance Cfs214 between floating gate 203 and silicon semiconductor substrate 201. Capacitance Ccf is determined by the thickness, area and permittivity of interpoly insulation film 208 between control gate 209 and floating gate 203. Capacitance Cfs is determined by the thickness, area and permittivity of tunnel oxide film 202 between floating gate 203 and silicon semiconductor substrate 201.
When memory cell 210 is an n type memory cell, the threshold voltage Vth of memory cell 210 can be made higher by the following manner. Potential difference between floating gate voltage Vfg and substrate voltage Vsub of the silicon semiconductor substrate is set to be Vfg&gt;Vsub, an electric field applied to tunnel oxide film 202 between floating gate 203 and silicon semiconductor substrate 201 is increased to be large enough to cause an N (Fowler-Nordheim) tunneling current, and electrons are injected and accumulated through tunnel oxide film 202 to floating gate 203. This is one method of injecting electrons to floating gate 203. There are also other methods of injecting electrons to floating gate 203.
Floating gate 203 is surrounded by some insulation film entirely. Therefore, it is not possible to control floating gate voltage Vfg by directly applying a voltage to floating gate 203. In order to change floating gate voltage Vfg, control gate voltage Vcg is changed. Floating gate voltage Vfg in the absence of any charges in floating gate 203 is represented by the following equation using control gate voltage Vcg, capacitance Ccf between control gate 209 and floating gate 203 and capacitance Cfs between floating gate 203 and semiconductor substrate 201. EQU Vfg=vcg.times.[Ccf.div.(Ccf+Cfs)] EQU Ccf.div.(Ccf+Cfs)=Cp
where Cp is generally referred to as a coupling ratio.
It can be understood from the equation above that when capacitance Ccf213 between control gate 209 and floating gate 203 is increased, that is, when coupling ratio Cp is made close to 1, it is possible to inject electrons through tunnel oxide film 202 to floating gate 203. Floating gate voltage Vfg necessary for increasing the electric field to be applied to tunnel oxide film 202 to that extent can be obtained without much increasing control gate voltage Vcg. The reason for this is that coupling ratio Cp is always not larger than 1, enhance when Cp becomes close to 1, difference between floating gate voltage Vfg and control gate voltage Vcg becomes smaller. Therefore, burden on the peripheral circuitry for generating control gate voltage Vcg can be reduced. As a result, the area for a high voltage generating circuit (a charge pump circuit) in the peripheral circuitry can be reduced and the chip area of the nonvolatile semiconductor memory device can be reduced.
In order to increase capacitance Ccf213 between control gate 209 and floating gate 203, the thickness of interpoly insulation film 203 may be reduced, the area of interpoly insulation film 208 in contact with control gate 209 and floating gate 203 may be increased, or permittivity of insulation film 208 may be increased. However, when the thickness of interpoly insulation film 208 is made thinner or a film having high permittivity is used other than silicon oxide film or silicon nitride film, retention failure is likely in which charges stored in floating gate 203 leak through interpoly insulation film 208 to control gate 209. Accordingly, generally, the area of interpoly insulation film 208 in contact with control gate 209 and floating gate 203 is increased. In order to increase the area of interpoly insulation film 208, not only the area of the upper surface of floating gate 203 but also areas on the side walls of floating gate 203 are utilized, so that the area of interpoly insulation film 208 in contact with control gate 209 and floating gate 203 is increased. For this reason, the upper surface of thick oxide film 206 is made lower by the thickness z than the upper surface of floating gate 203 so as to utilize the area of the side walls on both sides of the floating gate 203.
Referring to FIG. 30, when thick oxide film 206 is wet etched much by hydrofluoric acid solution and the side walls of floating gate 203 are exposed so as to increase the area of interpoly insulation 208 in contact with control gate 209 and floating gate 203, there arises the following problem. More specifically, it is likely that the thick oxide film 206 is etched too much by variations in process parameters such as variation in etching rate of hydrofluoric acid solution, variation of etching rate caused by film property, state of the thick oxide film 206 to be etched, and so on. As a result, the upper surface of thick oxide film 206 comes to be positioned lower than the bottom surface of floating gate 203. Eventually, the thick oxide film 206 comes to have such a shape as shown FIG. 30 forming a parasitic transistor 212. Parasitic transistor 212 is formed by control gate 209 serving as a gate electrode, interpoly insulation film 208 as a gate oxide film, the portion A in the figure serving as a channel region, and upper and lower portions on the sheet, not shown, serving as a pair of source/drain regions. The threshold voltage Vth of memory cell 210 as a single transistor is high. Further, in memory cell 210 as a single transistor, only a current not higher than the current value enabling determination of current flow in the channel of the memory cell flows. Even in such a case, a current not lower than the current value allowing determination of a current flow in the channel of the memory cell may flow in the parasitic transistor 212 when a certain voltage is applied to control gate 209. In such a case, the memory cell as a whole malfunctions.
The first problem of the second prior art example will be described in the following.
According to the second prior art example, referring to FIG. 22, silicon nitride film 211 is deposited on floating gate 203. Therefore, the problem experienced by the first prior art example, that is, plasma damage at the surface of floating gate and inner portion of floating gate near the surface can be solved. Further, physical and chemical damages at the upper surface of floating gate and inner portion of floating gate near the upper surface by the etching under CMP method can be avoided. Further, contamination by carbon or the like from the resist formed of an organic substance, can be avoided.
However, referring to FIGS. 26 and 27, when silicon nitride film 211 is removed by hot phosphoric acid, floating gate 203 is exposed to the hot phosphoric acid, so that the surface of the floating gate 203 is made rough and comes to have small recesses and protrusions. Roughness and small protrusions and recesses of the upper surface of the floating gate lead to electric field concentration, possibly causing unsatisfactory retention.
The second problem of the second prior art example is as follows.
More specifically, in the second prior art example, in order to increase coupling ratio Cp, that is, in order to increase capacitance Ccf between control gate 209 and floating gate 203, the upper surface of thick oxide film 206 is made lower by the thickness z than the upper surface of floating gate 203 so as to increase the area of interpoly insulation film 208 in contact with control gate 209 and floating gate 203 by twice the thickness z of the side walls (both sides) of the exposed floating gate 203.
In this manner, capacitance Ccf between control gate 209 and floating gate 203 is increased.
However, when thick oxide 206 protruding upper than the upper surface of floating gate 203 is etched too much by using hydrofluoric acid solution as shown in FIG. 27, the upper surface of thick oxide film 206 may possibly be lower than the bottom surface of floating gate 203. In that case, parasitic transistor 212 shown in FIG. 30 is formed and memory cell 212 as a whole does not function properly.